The present disclosure relates generally to a multi-tier architecture that facilitates development of Media Access Control (MAC) interfaces compliant with time-synchronization protocols such as the IEEE 1588 PTP protocol.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
Networks of electronic devices in which a common communication channel is shared usually implement conflict-avoidance protocols for accessing the channel. As an example, devices compliant with IEEE 802.3 Ethernet protocols usually include a Media Access Control (MAC) layer responsible for sending, receiving and routing packets within the network according to the Media Access Control protocol. This layer may be implemented in MAC circuitry located in the network interface. Due to uncertainties inherent to the protocol, delays in the communication between two devices may change. Therefore, specialized mechanisms and methods to provide synchronization between internal clocks of electronic devices connected to the network may be employed if such synchronization is desired.
Protocols designed to provide such synchronization, such as the IEEE 1588 Precision Time Protocol (PTP), are based on an exchange of timestamps or requests between devices. As specified in these protocols, the exchange and processing of the information allow accurate measurement of communication delays and clock offsets, which can be used for synchronization between the connected devices. For accuracy in this measurement, circuitry responsible for parsing IEEE 1588 packets and generating timestamps are implemented via hardware within the network circuitry of the electronic device.
The resulting design leads to an architecture in which the IEEE 1588 circuitry development is closely tied to the MAC circuitry development. For example, IEEE 1588 protocol operations are carried out at the data path width of the internal MAC circuitry, which can be, for example, 8 bit, 32 bit, 54 bit, 128 bit or 256 bit. As a result, changes in the design of the MAC circuitry may involve a redesign of the circuitry responsible for IEEE 1588 operations. Similarly, changes to the IEEE 1588 specification may involve a redesign of each of the existing versions of MAC circuitry. As a result, significant inefficiencies in resource usage, product management, validation and verification processes have been observed in the life cycle of IEEE 1588-compliant network circuitry.